1. Field of the Invention
The present invention generally relates to the manufacturing of MOS transistors in a semiconductor substrate. More specifically, the present invention relates to the manufacturing of transistors having a gate of a length smaller than 100 nm.
2. Discussion of the Related Art
Certain MOS transistors comprise pockets of a same first conductivity type but more heavily doped than the substrate, at the surface of which are formed lightly-doped regions (LDD) of the second conductivity type and heavily-doped surface regions (HDD) of the second conductivity type.
The present invention will be described hereafter in relation with the forming of an N-channel MOS transistor formed in a P-type doped silicon substrate. FIG. 1 illustrates, in a partial simplified cross-section view, an N-channel MOS transistor at an intermediary step of its manufacturing according to a known method.
The method starts with the definition of a gate G insulated from the surface of substrate 1 by a thin insulator 3. The method continues with the forming by implantation, at the substrate surface, of N-type lightly-doped regions (LDD) 4 on either side of gate G. In this implantation, gate G is used as an implantation mask. Pockets 6 of the same conductivity type as substrate 1 are also formed by implantation. The pockets are more heavily doped than the substrate, but less heavily than regions 4. Pockets 6 are formed between regions 4 and substrate 1. The pockets are generally formed, as illustrated in FIG. 1, along the entire junction between the substrate and regions 4, gate G being also used as an implantation mask.
The two successive implantations of the dopants of regions 4 and of pockets 6 are performed in any order.
The same diffusion anneal during which the dopants of regions 4 and of pockets 6 diffuse to provide the structure of FIG. 1 is then performed. This anneal can be performed at the end of the transistor forming process, after the implantation (not shown) of N-type dopants at the surface of regions 4 to form heavily-doped drain and source regions (HDD).
FIG. 2 schematically illustrates the doping profiles of the structure of FIG. 1 after the diffusion anneal. The abscissa axis corresponds to horizontal direction X of FIG. 1. As described previously, channel region 8 underlying gate G exhibits a small P-type doping and is separated from LDD lightly-doped N-type regions 4 by superficial portions of pockets 6 more heavily P-type doped than substrate 1, but less heavily doped than regions 4. As an example, the doping of substrate 1 and of channel region 8 is on the order of from 1015 to 1018 at·cm−3, the surface doping of regions 4 is on the order of from 1018 to 1020 at·cm−3, and the doping of pockets 6 is from 1016 to 1019 at·cm−3.
Pockets 6 are often used in transistors with small gate lengths to limit uncontrolled untimely switching problems imputed to so-called short channel effects. Such short channel effects are due to the diffusion of the dopants of regions 4 under gate G. Indeed, in the anneal performed to obtain regions 4 of an appropriate depth d, on the order of 20 nm, the dopants also diffuse under gate G with a diffusion length W. In operation, in the absence of pockets 6, in a biasing of regions 4, space charge areas create between regions 4 and substrate 1. Such space charge areas mostly extend into substrate 1, more lightly doped than regions 4. When gate G is narrow, the space charge areas extend until they cover each other. The control of the channel establishment by the gate is then lost.
The presence of pockets 6 more heavily P-type doped than substrate 1 enables limiting the extent of the space charge areas to these pockets. This enables keeping, in substrate 1, a channel area 8 controlled by the sole biasing of gate G.
FIG. 3 schematically illustrates a type of known implantation device 30 with a magnetic deviation dopant species selection. A target is ionized in a cation source IS. The cation flow coming out of chamber IS is accelerated under a potential difference V. The obtained beam is collimated by a diaphragm D and sent into a magnetic deviation chamber MAGDEV where a cation mass discrimination is performed. Indeed, from a given target, a great number of cations is obtained. For example, for a P-type doping by means of boron, a source of boron trifluoride BF3 which provides, on ionization, cations B+, BF+, BF2+, and BF3+, is used. Magnetic deviation circuit MAGDEV enables only selecting the cations B+ which are sent to wafer 31 to be implanted. Thus, fundamentally, this type of device only enables implanting a single species (ionized atom or molecule) and dopant type.
FIG. 4 schematically illustrates another type of known plasma implantation device 40 generally used for extremely fine implantations. In device 40, a plasma 43 is created in the vicinity of a wafer 41. Plasma 43 comprises, in the form of cations that can be dispersed in an inert carrier gas such as argon or xenon, a species to be implanted. The wafer is biased to a negative reference voltage Vs. Then, the cations implant into wafer 41. Device 40 enables performing implantations at reduced implantation powers with respect to device 30. The penetration depths of the doping cations is then reduced.
Whatever the used implantation device 30 or 40, two successive N-type and P-type implantations are performed, in an indifferent order, to obtain the structure of FIG. 1 and the diffusion profiles illustrated in FIG. 2.
A disadvantage of such a MOS transistor forming method lies in the long times linked to the implantations and the costs of use of two separated implanters.